Data buses are used in integrated circuits (ICs) to transfer data between master devices, such as user-controlled microprocessors, and slave devices controlling peripheral devices, such as memories and the like. Such an IC is often referred to as a system-on-chip (SOC). Some SOCs support multiple processors and are referred to as multi-core SOCs.
In many cases, the processors of a multi-core SOC either do not communicate with each other or use a single, very simple communications mechanism. However, in some cases a multi-core SOC might be configured with two or more processors that either operate in different formats or use a variety of communications mechanisms with each other. In such cases, the SOC is designed to support the requirements of each processor to be coupled by the SOC. For example, if the processors require different hardware resources, or use them in diverse manners, the SOC must be designed to accommodate all such requirements and uses. Hence, the SOC is designed to accommodate various communications hardware requirements, such as the number and depth of first-in first-out memories (FIFOs), flag and interrupt registers and centralized random-access memories (RAMs), as well as other requirements such as bus protocols, data formats (including endianess), datapath widths, bus frequencies and synchronous/asynchronous communication, to name a few.
Consequently, multi-core SOCs are designed and fabricated for selected hardware and software requirements of the processors, and are not easily adapted to other processor hardware or software requirements. The multi-core SOCs are not easily reconfigurable or programmable to accept processors with different requirements.